Formal verification of multiplier circuits using computer algebra

A Formal Approach to Designing Arithmetic Circuits over Galois Fields Using Symbolic Computer Algebra

This paper proposes a formal approach to designing arithmetic circuits over Galois Fields (GFs). Our method represents a GF arithmetic circuit by a hierarchical graph structure specified by variables and arithmetic formulae over GFs. The proposed circuit description is applicable to anyGF (p) (p ≥ 2) arithmetic and is formally verified by symbolic computation techniques such as polynomial reduc...

Design and formal verification of DZMBE+

In this paper, a new broadcast encryption scheme is presented based on threshold secret sharing and secure multiparty computation. This scheme is maintained to be dynamic in that a broadcaster can broadcast a message to any of the dynamic groups of users in the system and it is also fair in the sense that no cheater is able to gain an unfair advantage over other users. Another important feature...

Formal verification of sequential circuits using reasoning techniques

Formal Verification of Digital Circuits Using Symbolic Ternary System Models

Ternary system modeling involves extending the traditional set of binary values f0; 1gwith a third value X indicating an unknown or indeterminate condition. By making this extension, we can model a wider range of circuit phenomena. We can also efficiently verify sequential circuits in which the effect of a given operation depends on only a subset of the total system state. This paper presents a...

Web Service Choreography Verification Using Z Formal Specification

Web Service Choreography Description Language (WS-CDL) describes and orchestrates the services interactions among multiple participants. WS-CDL verification is essential since the interactions would lead to mismatches. Existing works verify the messages ordering, the flow of messages, and the expected results from collaborations. In this paper, we present a Z specification of WS-CDL. Besides ve...